In a nonvolatile semiconductor memory device having a structure having floating gates in a charging storage layer such as a NAND flash memory, the size of a peripheral transistor formed in a peripheral circuit portion is required to be reduced according to shrink trend of a memory cell unit.
When the width of the peripheral transistor is reduced, the peripheral transistor is largely affected by a parasitic transistor formed at an end portion of an element region (active area) arranged in proximity to an element isolation region, and this brings about a decrease of a threshold value and an increase of an off-leakage current caused by the decrease of the threshold value. The reason why the parasitic transistor is formed at the end portion of the element region is considered to be caused by mainly fixed charges in insulating film embedded within the element isolation region and charging to the element isolation region during manufacturing process.